Semiconductor integrated circuit device

ABSTRACT

An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation of PCT International ApplicationPCT/JP2010/007390 filed on Dec. 21, 2010, which claims priority toJapanese Patent Application No. 2010-036599 filed on Feb. 22, 2010. Thedisclosures of these applications including the specifications, thedrawings, and the claims are hereby incorporated by reference in theirentirety.

BACKGROUND

The present disclosure relates to semiconductor integrated circuitdevices, particularly relates to a configuration connecting an internalcircuit, an electrode pad formed above a circuit block, and an ESDprotection circuit which protects the internal circuit from damage dueto electrostatic discharge (ESD).

In recent years, with higher integration of circuits, the number of pinsof the semiconductor integrated circuit devices is increasing. Tocorrespond to such an increase in the number of pins, a technique ofarranging electrode pads in a matrix is suggested in, for example,Japanese Patent Publication No. H05-218204.

In general, an ESD protection circuit is positioned below an electrodepad. Thus, if many electrode pads are positioned above the circuitblock, the ESD protection circuits may obstruct the circuitconfiguration in the circuit block, and this may result in problems,such as an increase in circuit area and high density of lines.

To solve the above problems, Japanese Patent Publication No.2001-237317, for example, discloses a structure in which the ESDprotection circuit is not positioned below the electrode pad, but ispositioned at a periphery of a semiconductor integrated circuit device.

SUMMARY

In general, an input/output circuit connected to an electrode pad ispositioned under the electrode pad. Thus, if the ESD protection circuitis positioned at the periphery of the semiconductor integrated circuitdevice as in Japanese Patent Publication No. 2001-237317, it does notobstruct the circuit configuration, but the length of the line forelectrically connecting the electrode pad and the ESD protection circuitmay be increased. As a result, a problem in which a surge current doesnot sufficiently flow in the ESD protection circuit, and theinput/output circuit is easily damaged, may be caused.

According to one aspect of the present disclosure, a semiconductorintegrated circuit device includes: a circuit block having an internalcircuit which is an input circuit, an output circuit, or an input/outputcircuit; an electrode pad provided above the circuit block, andelectrically connected to the internal circuit; and an electrostaticdischarge (ESD) protection circuit electrically connected to theelectrode pad, wherein a junction point is provided at a connection lineconnecting the electrode pad to the internal circuit and the ESDprotection circuit; the connection line includes a first line connectingthe electrode pad and the junction point, a second line connecting thejunction point and the internal circuit, and a third line connecting thejunction point and the ESD protection circuit; and the junction point ispositioned at a location which is closer to the ESD protection circuitthan to the electrode pad.

According to this aspect of the present disclosure, of the connectionline connecting the electrode pad to the internal circuit and the ESDprotection circuit, the first line connecting the electrode pad and thejunction point is a shared line for connecting the electrode pad and theinternal circuit, and for connecting the electrode pad and the ESDprotection circuit. Since the junction point is positioned at a locationcloser to the ESD protection circuit than to the electrode pad, aresistance value of the third line connecting the junction point and theESD protection circuit is small. Thus, a surge current applied to theelectrode pad can easily flow in the ESD protection circuit. As aresult, it is possible to prevent damage of the internal circuit.

In a semiconductor integrated circuit device according to the presentdisclosure in which an electrode pad is positioned above a circuitblock, a surge current applied to the electrode pad can easily flow inan ESD protection circuit, and therefore, it is possible to preventdamage of an internal circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram which schematically shows a configuration ofa semiconductor integrated circuit device according to the firstembodiment.

FIG. 2 is a graph which shows properties of an ESD protection circuit.

FIG. 3 shows a configuration of a semiconductor integrated circuitdevice according to the second embodiment.

FIG. 4 is a diagram for explaining an outermost electrode pad.

FIG. 5 shows a configuration of a semiconductor integrated circuitdevice according to the third embodiment.

FIG. 6 shows a configuration of a semiconductor integrated circuitdevice according to a variation of the third embodiment.

FIG. 7 shows a configuration of a semiconductor integrated circuitdevice according to the fourth embodiment.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in detail belowbased on the drawings.

First Embodiment

FIG. 1 is a circuit diagram which schematically shows a configuration ofa semiconductor integrated circuit device according to the firstembodiment. The semiconductor integrated circuit device according to thepresent embodiment includes a circuit block in which an input circuit105 as an internal circuit is provided, an electrode pad 101 and a GNDelectrode pad 112 which are provided above the circuit block and areelectrically connected to the input circuit 105, and an ESD protectioncircuit 108 which is electrically connected to the electrode pad 101 andthe GND electrode pad 112 to protect the circuit block from damage dueto electrostatic discharge (ESD). In the configuration in FIG. 1, theESD protection circuit 108 is comprised of an N type MOS transistor.

A junction point A103 is provided on a connection line connecting theelectrode pad 101 to the input circuit 105 and the ESD protectioncircuit 108. A junction point B109 is provided on a connection lineconnecting the GND electrode pad 112 to the input circuit 105 and theESD protection circuit 108.

Specifically, the electrode pad 101 and a drain region of the ESDprotection circuit 108 comprised of the N type MOS transistor areconnected to each other by a line 102 as a first line connecting theelectrode pad 101 and the junction point A103, and a line 106 as a thirdline connecting the junction point A103 and the ESD protection circuit108. The GND electrode pad 112 and a source region of the ESD protectioncircuit 108 are connected to each other by a line 111 as a first lineconnecting the GND electrode pad 112 and the junction point B109, and aline 107 as a third line connecting the junction point B109 and the ESDprotection circuit 108.

A gate of the input circuit 105 is connected to the electrode pad 101 bythe line 102 connecting the electrode pad 101 and the junction pointA103, and a line 104 as a second line connecting the junction point A103and the input circuit 105. A source region of the input circuit 105 isconnected to the GND electrode pad 112 by the line 111 connecting theGND electrode pad 112 and the junction point B109, and a line 110 as asecond line connecting the junction point B109 and the input circuit105.

The junction point A103 is positioned at a location closer to the ESDprotection circuit 108 than to the electrode pad 101. The junction pointB109 is positioned at a location closer to the ESD protection circuit108 than to the GND electrode pad 112.

FIG. 2 is a graph which shows properties of the ESD protection circuit108. In FIG. 2, voltages (hereinafter referred to as internal voltages)applied to the ESD protection circuit 108 and the input circuit 105 whena surge voltage is applied to the electrode pad 101 is represented by Xaxis, and a current which flows at the voltage application isrepresented by Y axis.

As shown in FIG. 2, in the case where a surge voltage is applied to theelectrode pad 101, the ESD protection circuit 108 is turned on when theinternal voltage is increased to “4A” voltage, and a current abruptlyflows in the ESD protection circuit 108 due to breakdowncharacteristics. The characteristics of the current which flows in theESD protection circuit 108 depend on a sum of resistance values(hereinafter referred to as ESD protection resistance values) of thelines 106, 107, i.e., the lines from the junction point A103 and thejunction point B109 to the ESD protection circuit 108. In the presentembodiment, the upper limit of the ESD protection resistance value whichneeds to be satisfied is called a reference resistance value.

Now, the lines whose resistances are calculated as the ESD protectionresistance value will be described.

The lines 102, 111 are shared lines for connecting the electrode pad 101and the GND electrode pad 112 to the input circuit 105 and to the ESDprotection circuit 108. Thus, it is clear that these lines can beomitted from consideration.

The lines 104, 110 can be considered as follows. That is, the size ofthe transistor of the ESD protection circuit 108 is adjusted, ingeneral, such that an operating voltage (which is almost the same as aninternal voltage) at the time of application of a reference surgevoltage is less than a withstand voltage of a gate oxide film of theinput circuit 105 as long as the ESD protection resistance value isequal to or less than a reference resistance value. Thus, even if theresistance values of the lines 104, 110 are 0Ω, the input circuit 105 isnot damaged by the application of the reference surge voltage as long asthe ESD protection resistance value is equal to or less than thereference resistance value. For this reason, the lines 104, 110 can alsobe omitted from consideration.

In FIG. 2, the inclination G1 represents the characteristics of acurrent flowing in the ESD protection circuit 108 when the ESDprotection resistance value is smaller than the reference resistancevalue. In the case represented by the inclination G1, the internalvoltage at the time of application of a surge voltage of 1000 V, forexample, is “4C” voltage, which is lower than “4B” voltage, i.e., thewithstand voltage of the input circuit 105. Thus, the input circuit 105is not damaged. On the other hand, the inclination G2 represents thecurrent characteristics when the ESD protection resistance value islarger than the reference resistance value. In the case represented bythe inclination G2, the internal voltage at the time of application of asurge voltage of 1000 V is “4D” voltage, which is larger than “4B”voltage, i.e., the withstand voltage of the gate oxide film. Thus, theinput circuit 105 is damaged. Here, the surge voltage of 1000 V isapplied as an example. However, the allowable surge voltage may beincreased because the smaller the ESD protection resistance value, themore current flows in the ESD protection circuit 108.

Specifically, the resistance values of the lines 102, 111 can be omittedfrom the calculation of the ESD protection resistance value by providingthe junction point A103 and the junction point B109 as shown in FIG. 1.Further, the lengths of the lines 106, 107, that is, the lengths fromthe junction point A103 and the junction point B109 to the ESDprotection circuit 108, are reduced by positioning the junction pointA103 and the junction point B109 at the locations closer to the ESDprotection circuit 108 than to the electrode pad 101 and the GNDelectrode pad 112. As a result, the ESD protection resistance value canbe reduced, and the allowable surge voltage is increased.

As described above, according to the present embodiment, the first lineconnecting the electrode pad and the junction point, the second lineconnecting the junction point and the input circuit, and the third lineconnecting the junction point and the ESD protection circuit, areprovided to position the junction point at a location closer to the ESDprotection circuit than to the electrode pad. As a result, the ESDprotection resistance value is reduced, and thus, easily satisfies thereference resistance value. Moreover, the allowable surge voltage isfurther increased.

Further, the smaller the resistance values of the lines 106, 107, themore current flows in the ESD protection circuit 108 at the applicationof the surge voltage. In contrast, the larger the resistance values ofthe lines 104, 110, the lower voltage is applied to the input circuit105. Thus, the allowable surge voltage is further increased. That is,according to the present embodiment, the allowable surge voltage can befurther increased by satisfying the following relationship, that is, aresistance value of the line from the junction point to the inputcircuit>a resistance value of the line from the junction point to theESD protection circuit (a resistance value of the second line>aresistance value of the third line). In general, the length of the lineand the resistance value are proportional to each other. Thus, if thefollowing relationship, that is, the length of the line from thejunction point to the input circuit>the length of the line from thejunction point to the ESD protection circuit (the length of the secondline>the length of the third line), is satisfied, the allowable surgevoltage is further increased without a need to check the resistancevalue.

Second Embodiment

FIG. 3 shows a configuration of a semiconductor integrated circuitdevice according to the second embodiment. In the semiconductorintegrated circuit device 201 shown in FIG. 3, electrode pads 22 arearranged above a circuit block 21. The reference character 2B is anenlarged view of the area 2A. As shown in the enlarged view 2B, an ESDprotection circuit 206 is positioned closer to the periphery of thesemiconductor integrated circuit device 201 than an electrode pad 202, aGND electrode pad 213, and an input circuit 208. A junction point A204is provided on a connection line connecting the electrode pad 202 to theinput circuit 208 and the ESD protection circuit 206. A junction pointB212 is provided on a connection line connecting the GND electrode pad213 to the input circuit 208 and the ESD protection circuit 206.

Specifically, the electrode pad 202 and a drain region of the ESDprotection circuit 206 comprised of an N type MOS transistor areconnected to each other by a line 203 as a first line connecting theelectrode pad 202 and the junction point A204, and a line 205 as a thirdline connecting the junction point A204 and the ESD protection circuit206. The GND electrode pad 213 and a source region of the ESD protectioncircuit 206 are connected to each other by a line 214 as a first lineconnecting the GND electrode pad 213 and the junction point B212, and aline 210 as a third line connecting the junction point B212 and the ESDprotection circuit 206.

A gate of the input circuit 208 is connected to the electrode pad 202 bythe line 203 connecting the electrode pad 202 and the junction pointA204, and a line 207 as a second line connecting the junction point A204and the input circuit 208. A source region of the input circuit 208 isconnected to the GND electrode pad 213 by the line 214 connecting theGND electrode pad 213 and the junction point B212, and a line 215 as asecond line connecting the junction point B212 and the input circuit208.

The junction point A204 and the junction point B212 are positioned atlocations between the ESD protection circuit 206 and the input circuit208. The junction point A204 and the junction point B212 are positionedat locations close to the periphery of the semiconductor integratedcircuit device 201, that is, closer to the ESD protection circuit 206than the input circuit 208. In this structure, routing of the lines 207,215 along the lengths W1, W2 is necessary. However, the lines 205, 210connecting the junction point A204 and the junction point B212 to theESD protection circuit 206 can be shorter, compared to the case in whichthe electrode pad 202 and the GND electrode pad 213 are connected to theinput circuit 208 by the shortest lines. As a result, the resistances ofthe lines 205, 210 can be reduced by the resistances of the lengths W1,W2, and the ESD protection resistance value can be reduced.

As described above, according to the present embodiment, the first lineconnecting the electrode pad and the junction point, the second lineconnecting the junction point and the input circuit, and the third lineconnecting the junction point and the ESD protection circuit, areprovided to position the ESD protection circuit at the periphery of thesemiconductor integrated circuit device, provide the junction point at alocation between the input circuit and the ESD protection circuit, andprovide routing of the second line, thereby making it possible to reducethe ESD protection resistance value.

Further, in FIG. 3, the lines whose resistances are calculated as theESD protection resistance value are the lines 205, 210. In FIG. 3, amongthe electrode pads of the semiconductor integrated circuit device 201,an outermost electrode pad is used as the GND electrode pad 213 to whichthe ESD protection circuit 206 is connected. The outermost electrode padis closest to the periphery of the semiconductor integrated circuitdevice 201, and therefore, the lines 210, 214 can be shorter compared tothe case in which an electrode pad which is not an outermost electrodepad is used as the GND electrode pad 213. As a result, it is possiblenot only to reduce the ESD protection resistance value, but also toprevent high density of the lines in the semiconductor integratedcircuit device 201.

Additional descriptions about the “outermost electrode pad” describedabove will be provided using FIG. 4.

In FIG. 4, among the electrode pads arranged above the semiconductorintegrated circuit device 221, an electrode pad to which the ESDprotection circuit is connected is an electrode pad 25 located above acircuit block 23. An electrode pad 24 located at the periphery of thesemiconductor integrated circuit device 221 is an electrode paddedicated to testing, which is used only for testing. Thus, in general,the ESD protection circuit is not connected to the electrode pad 24. Theterm “outermost electrode pad” as used herein refers to an outermostelectrode pad among the electrode pads arranged above the circuit block.

The electrode pads 22 are arranged in a matrix in FIG. 3, but do notnecessarily have to be arranged in a perfect matrix. For example, someof the electrode pads 22 may not be aligned or may be omitted.

Third Embodiment

FIG. 5 shows a configuration of a semiconductor integrated circuitdevice according to the third embodiment. In the semiconductorintegrated circuit device 301 shown in FIG. 5, electrode pads 32 arearranged above a circuit block 31. The reference character 3B is anenlarged view of the area 3A. As shown in the enlarged view 3B, an ESDprotection circuit 306 is positioned at a location in a circuit block 31that is different from an internal circuit area 304 in which an inputcircuit 305 is provided. A junction point A308 is provided on aconnection line connecting an electrode pad 303 to the input circuit 305and the ESD protection circuit 306. A junction point B312 is provided ona connection line connecting a GND electrode pad 313 to the inputcircuit 305 and the ESD protection circuit 306.

Specifically, the electrode pad 303 and a drain region of the ESDprotection circuit 306 comprised of an N type MOS transistor areconnected to each other by a line 307 as a first line connecting theelectrode pad 303 and the junction point A308, and a line 310 as a thirdline connecting the junction point A308 and the ESD protection circuit306. The GND electrode pad 313 and a source region of the ESD protectioncircuit 306 are connected to each other by a line 314 as a first lineconnecting the GND electrode pad 313 and the junction point B312, and aline 311 as a third line connecting the junction point B312 and the ESDprotection circuit 306.

A gate of the input circuit 305 is connected to the electrode pad 303 bythe line 307 connecting the electrode pad 303 and the junction pointA308, and a line 309 as a second line connecting the junction point A308and the input circuit 305. A source region of the input circuit 305 isconnected to the GND electrode pad 313 by the line 314 connecting theGND electrode pad 313 and the junction point B312, and a line 315 as asecond line connecting the junction point B312 and the input circuit305.

The ESD protection circuit 306 is positioned in the circuit block 31 inwhich the input circuit 305 is also positioned, but in a location whichis different from the internal circuit area 304 where the input circuit305 is provided, as shown in FIG. 5. In this structure, the ESDprotection circuit 306 can be positioned close to the junction pointA308 and the junction point B312, without obstructing the configurationand the lines of an internal circuit in the circuit block 31. Further,the ESD protection circuit 306 can be positioned closer to the electrodepad 303 and the GND electrode pad 313, compared to the case in which theESD protection circuit is positioned at the periphery of thesemiconductor integrated circuit device. As a result, the routing of thelines 310, 311 can be reduced, and therefore, the ESD protectionresistance value can be reduced. The allowable surge voltage is furtherincreased.

As described above, according to the present embodiment, the first lineconnecting the electrode pad and the junction point, the second lineconnecting the junction point and the input circuit, and the third lineconnecting the junction point and the ESD protection circuit, areprovided to position the ESD protection circuit in the circuit block. Inthis structure, the third line can be provided in the circuit block, andthus, it is possible to reduce the length of the line, compared to thecase in which the ESD protection circuit is positioned at the peripheryof the semiconductor integrated circuit device. As a result, the ESDprotection resistance value can be reduced.

Moreover, in general, internal circuits are densely provided near acentral portion of the circuit block 31, whereas the internal circuitsare less densely provided near the frame of the circuit block 31. Thus,in the present embodiment, it is preferable to position the ESDprotection circuit 306 at a location in the circuit block 31 which iscloser to an outside than the internal circuit area 304. As a result,the ESD protection circuit 306 is not likely to obstruct the internalcircuit.

FIG. 6 shows a configuration of a semiconductor integrated circuitdevice according to a variation of the present embodiment. In theconfiguration of FIG. 6, not the GND electrode pad 313, but an electrodepad 321 adjacent to the ESD protection circuit 306 is used as the GNDelectrode pad. With this structure, the length of the connection line311 which is connected to the source of the ESD protection circuit 306can be shorter, compared to the structure shown in FIG. 5. As a result,the ESD protection resistance value can be reduced, and the allowablesurge voltage is further increased.

In FIG. 6, the GND electrode pad 321 is located above the circuit block31, but may be at any location as long as the electrode pad is adjacentto the ESD protection circuit 306, or at a location which overlaps withthe ESD protection circuit 306.

In FIG. 5 and FIG. 6, the electrode pads 32 are arranged in a matrix,but do not necessarily have to be arranged in a perfect matrix. Forexample, some of the electrode pads may not be aligned or may beomitted.

Fourth Embodiment

FIG. 7 shows a configuration of a semiconductor integrated circuitdevice according to the fourth embodiment. In the semiconductorintegrated circuit device 401 shown in FIG. 7, electrode pads 42 arearranged above the circuit block 41. The reference character 4B is anenlarged view of the area 4A. As shown in the enlarged view 4B, an ESDprotection circuit 404 is positioned adjacent to an input circuit 405. Ajunction point A407 is provided on a connection line connecting anelectrode pad 403 to the input circuit 405 and the ESD protectioncircuit 404. A junction point B412 is provided on a connection lineconnecting a GND electrode pad 410 to the input circuit 405 and the ESDprotection circuit 404.

Specifically, the electrode pad 403 and a drain region of the ESDprotection circuit 404 comprised of an N type MOS transistor areconnected to each other by a line 406 as a first line connecting theelectrode pad 403 and the junction point A407, and a line 408 as a thirdline connecting the junction point A407 and the ESD protection circuit404. The GND electrode pad 410 and a source region of the ESD protectioncircuit 404 are connected to each other by a line 413 as a first lineconnecting the GND electrode pad 410 and the junction point B412, and aline 411 as a third line connecting the junction point B412 and the ESDprotection circuit 404.

A gate of the input circuit 405 is connected to the electrode pad 403 bythe line 406 connecting the electrode pad 403 and the junction pointA407, and a line 409 as a second line connecting the junction point A407and the input circuit 405. A source region of the input circuit 405 isconnected to the GND electrode pad 410 by the line 413 connecting theGND electrode pad 410 and the junction point B412, and a line 414 as asecond line connecting the junction point B412 and the input circuit405.

The routing of the lines 411, 414 and the lines 408, 409 can beshortened by positioning the ESD protection circuit 404 at a locationadjacent to the input circuit 405 as shown in FIG. 7. That is, both ofthe length from the electrode pad to the input circuit, and the lengthfrom the electrode pad to the ESD protection circuit are reduced,compared to the third embodiment. This means that it is possible toreduce not only the ESD protection resistance value, but also theresistance values of the lines connected to the input circuit. Also,less line resources are necessary.

As described above, according to the present embodiment, the first lineconnecting the electrode pad and the junction point, the second lineconnecting the junction point and the input circuit, and the third lineconnecting the junction point and the ESD protection circuit, areprovided to position the ESD protection circuit at a location adjacentto the input circuit in the circuit block. With this structure, it ispossible to reduce not only the ESD protection resistance value, butalso the resistance values of the lines connected to the input circuit.Also, less line resources are necessary.

In the above embodiments, the junction points are provided at twolocations (the junction point A and the junction point B) as examples,but the same advantages can be obtained even if one of the two junctionpoints is provided.

In the above embodiments, the ESD protection circuit is comprised of anN type MOS transistor whose gate voltage is fixed to a ground voltage,but may be comprised of a P type MOS transistor. In this case, needlessto say, the GND electrode pad serves as a power source electrode pad.

In the above embodiments, an input circuit comprised of a MOS transistorhaving a gate electrode to which a line from an external connectionterminal is connected is shown as an example internal circuit to whichthe electrode pads are connected. The same advantages can be obtainedeven in the case where the input circuit is replaced with an outputcircuit comprised of a MOS transistor having a drain region to which theexternal connection terminal is connected, as the internal circuit towhich the electrode pads are connected. Alternatively, an input/outputcircuit may be used as the internal circuit, instead of using an inputcircuit and an output circuit.

The same advantages can be obtained even in the case where the ESDprotection circuit is comprised not of a MOS transistor, but of a diode,for example, or in the case where the internal circuit is comprised notof a MOS transistor, but of another element.

In the present disclosure, it is possible to prevent an internal circuitfrom being damaged by a surge voltage. Thus, the present disclosure isadvantageous in terms of increasing, for example, durability of asemiconductor integrated circuit device.

1-9. (canceled)
 10. A semiconductor integrated circuit device,comprising: a circuit block having an electrostatic discharge (ESD)protection circuit and an internal circuit which is an input circuit, anoutput circuit, or an input/output circuit; an electrode pad providedabove the circuit block, and electrically connected to the internalcircuit; and a peripheral portion located outside of the circuit block;and a connection line connecting the electrode pad to the internalcircuit and the ESD protection circuit and having a junction pointthereon, wherein: the connection line includes a first line connectingthe electrode pad and the junction point, a second line connecting thejunction point and the internal circuit, and a third line connecting thejunction point and the ESD protection circuit, the junction point islocated between the ESD protection circuit and the internal circuit in afirst direction in a plane view, the junction point is positioned at alocation which is closer to the ESD protection circuit than to theinternal circuit in the first direction in the plane view, the circuitblock includes an internal circuit area in which the internal circuit isprovided, and the ESD protection circuit is provided outside of theinternal circuit area and is separated from the internal circuit. 11.The semiconductor integrated circuit device of claim 10, wherein aresistance value of the third line is smaller than a resistance value ofthe second line.
 12. The semiconductor integrated circuit device ofclaim 10, wherein the second line is longer than the third line.
 13. Thesemiconductor integrated circuit device of claim 10, wherein the ESDprotection circuit is positioned at a location which is closer to anedge of the circuit block than the internal circuit area.
 14. Thesemiconductor integrated circuit device of claim 10, wherein theelectrode pad connected to the ESD protection circuit is adjacent to theESD protection circuit, or at a location which overlaps with the ESDprotection circuit.